To help those who are very familiar with Verilog to get into SystemC easier, I took some time and made this list. More content is to be added later on.
| Verilog | SystemC | |
| Module Define | module module_name (
input wire clk, input wire rst_n, input wire we, input wire [31:0] din, output wire [31:0] dout, output reg ready ); wire[7:0] a; wire[7:0] b; reg[31:0] mem[0:1023]; reg[31:0] r; dut u_dut ( .a (a), .b (b) ); assign dout = din; always@(posedge clk or negedge rst_n) begin if (!rst_n) begin: din_delay r <= 0; end else begin r <= din; end end endmodule |
// File: module_name.h
#ifndef _MODULE_NAME_H #define _MODULE_NAME_H #include <systemc.h> #include “dut.h” SC_MODULE(module_name) { sc_in_clk clk; sc_in<sc_uint<1> > rst; sc_in<sc_uint<1> > we; sc_in<sc_uint<32> > din; sc_out<sc_uint<32> > dout; sc_out<sc_uint<1> > ready; sc_uint<8> a; sc_uint<8> b; int mem[1024]; int r; void din_delay(); void do_pass(); dut u_dut; SC_CTOR(module_name) { u_dut.a(a); u_dut.b(b); SC_METHOD(do_pass); sensitive<<din; SC_THREAD(din_delay); sensitive_pos(clk); sensitive_neg(rst_n); } }; #endif // File: module_name.cpp void din_delay() { if (!rst_n) { r = 0; } else { r=din; } } void do_pass() { dout = din; } |
| Macro Define | `define NAME 123 | #define NAME 123 |
| Comment | // This is a comment | // This is a comment |
| Clock Define | reg clk
initial begin clk = 0; #50; forever #20 clk = ~clk; end |
sc_clock clk(“clk”, 40, SC_NS, 0.5, 50,SC_NS, true);
// “clk” is clock name // 40 is clock period // 0.5 is the duty rate // 50 is the start time // true means posedge first |
| Delay | #20ns | wait(20, SC_NS); |
| Time Scale | `timescale 1ns/1ps | sc_set_default_time_unit(1,SC_NS);
sc_set_time_resolution(1,SC_PS); // must be power of 10 // this is the default setting |
| Run Time | $time | sc_time_stamp() // use for print, text type
sc_simulation_time(); // use for calculation, double type |
| Combinational Logics | assign c = a + b;
always@(*) begin c = a + b; end |
SC_CTOR(module) {
SC_METHOD(comb); sensitive << a << b; } void comb() { c = a + b; } |
| Sequential Logics | always@(posedge clk or negedge rst_n) begin
if (!rst_n) begin out = 0; end else begin out = in; end end |
SC_CTOR(module) {
SC_CTHREAD(dff, clock.pos()); watching(rst_n.delayed()==0); } void dff() { if(rst_n==0) out = 0; while(1) { out = in; wait(); } } |
| Testbench | module top;
reg a,b,f; reg clk; initial begin clk = 0; forever #10 clk = ~clk end dut u_dut ( .a(a), .b(b), .f(f) ); initial begin dumpfile(“dut.vcd”); dumpvars(0,u_dut); dumpon; #200; $finish; end initial begin end endmodule |
#include “dut.h”
#include “tb.h” int sc_main (int i, char* av[]) { sc_uint<32> a, b, f; sc_clock clk(“clk”, 20, SC_NS); dut u_dut(“dut”); u_dut.a(a); u_dut.b(b); u_dut f(f); tb tb(“tb”); tb.clk(clk); tb.a(a) tb.b(b); tb.f(f); sc_trace_file *tf = sc_create_vdc_trace_file(“dut”); sc_trace(tf,u_dut.a,”a”); sc_trace(tf,u_dut.b,”b”); sc_trace(tf,u_dut.f,”f”); sc_start(200); sc_close_vdc_trace_file(tf); return 0; } |
| Bit Joins | {a[13:2],b} | (a.range(13,2),b) |
| Bit Operation | &a
| a ^ a |
a.and_reduce()
a.or_reduce() a.xor_reduce() |
| Simulation Control | $finish | sc_stop(); |
