VHDL – Where Two Linguists Met

Programming Languages, SystemVerilog, Verilog, VHDLSunday August 7th, 2016Wednesday November 29th, 2017

Useful Skills of Vim While Coding Verilog

1. 前言其实很早之前就应该写这篇文章了，只是最近太忙了。这几天看到我只列了一个空标题在这里都有好几个人点进来看过了，感觉做得挺不厚道，想想还是先写一点吧，一方面也是为了表明本文绝对是干货满满，值得期待的，废话不多说了，进入正文。 +140

Idea, Verilog, VHDLSaturday November 14th, 2015Saturday June 11th, 2016

How To Use Cadence LEC For Logic Equivalence Check

Conformal ® LEC Logic Equivalence Checker is a trade mark registered by Cadence. I use this tool very often lately to make sure the logic equivalence between RTL code written in both VHDL and Verilog languages. As there are not many tutorials online that talk about this tool, I have to had spent quit a […]

Idea, Verilog, VHDLMonday November 2nd, 2015Saturday November 14th, 2015

How To Mix VHDL And Verilog In Simulation

I will talk about this topic later. Basically, If you are using VCS, you will need to map the codes that was written in different languages into different libraries by using engines dedicated for different languages before you run any simulation. 00

Idea, Programming Languages, Verilog, VHDLSunday October 25th, 2015Wednesday May 11th, 2016

How To Convert VHDL To Verilog

It is said that, when it comes to the favourite digital RTL design language, most companies in the North America prefer Verilog, whereas many of their European counterparts will choose VHDL. Personally, I know Verilog better than VHDL. More specifically, I could only read VHDL code but not write it. So if I need to […]

SystemC, SystemVerilog, Verilog, VHDLFriday February 27th, 2015Saturday February 4th, 2017

The Knowledge Base Of A Qualified IC Design Engineer

When I just graduated from school, I deemed myself as an already qualified digital IC design engineer. However, I soon learnt how stupid I was once I started my career as an engineer. I have seen many great engineers in companies, and I have learnt a lot from them. In this article, I would love […]