Conformal ® LEC Logic Equivalence Checker is a trade mark registered by Cadence. I use this tool very often lately to make sure the logic equivalence between RTL code written in both VHDL and Verilog languages. As there are not many tutorials online that talk about this tool, I have to had spent quit a lot of time to go through the official user menu. In this article, I'd like to give you a step by step guideline to let you know how to use this tool to compare the design and eliminate the non-equivalence key points. Regarding to some specific tricky problems that I suppose most of you might encounter while doing cross-up comparison between VHDL and Verilog, I will list out all solutions that I found to resolve them.
Now first is the main script
[source lang="Tcl"]
vpxmode
reset
add notranslate modules a b c d
set naming rule -instance "%s" "%s_%d" "%s"
set naming rule -variable "%s" "%s" "%s"
set naming rule -mdportflatten -mdport_bitblast
set naming rule -parameter ""
set naming rule -instance_array "%s_%d"
set naming rule -enable_unnamed_blk_naming
add search path /some_path/some_dir
read design -golden -sensitive -norangeconstraint -continuousassignment bidirectional -nokeep_unreach -nosupply -lastmod -noelab \
-systemverilog -mapfile some_lib1 \
/some_path/some_dir/some_file1.v \
/some_path/some_dir/some_file2.v \
\
-systemverilog -mapfile some_lib2 \
/some_path/some_dir/some_file3.v \
/some_path/some_dir/some_file4.v \
\
read design -golden -continuousassignment bidirectional -norangeconstraint -nokeep_unreach -lastmod -noelab \
-vhdl 93 -mapfile some_lib1 \
/some_path/some_dir/some_file1.vhdl \
/some_path/some_dir/some_file2.vhdl \
\
-vhdl 93 -mapfile some_lib2 \
/some_path/some_dir/some_file3.vhdl \
/some_path/some_dir/some_file4.vhdl \
\
elaborate design -golden -root top_module_name
checkpoint a.ckpt -replace
add search path /some_path/some_dir
read design -revised -sensitive -norangeconstraint -continuousassignment bidirectional -nokeep_unreach -nosupply -lastmod -noelab \
-systemverilog -mapfile some_lib1 \
/some_path/some_dir/some_file1.v \
/some_path/some_dir/some_file2.v \
\
-systemverilog -mapfile some_lib2 \
/some_path/some_dir/some_file3.v \
/some_path/some_dir/some_file4.v \
\
read design -revised -continuousassignment bidirectional -norangeconstraint -nokeep_unreach -lastmod -noelab \
-vhdl 93 -mapfile some_lib1 \
/some_path/some_dir/some_file1.vhdl \
/some_path/some_dir/some_file2.vhdl \
\
-vhdl 93 -mapfile some_lib2 \
/some_path/some_dir/some_file3.vhdl \
/some_path/some_dir/some_file4.vhdl \
\
elaborate design -revised -root top_module_name
checkpoint b.ckpt -replace
report design data
report black box
uniquify -all -nolib
set flatten model -seq_constant -seq_constant_x_to 0
set flatten model -nodff_to_dlat_zero -nodff_to_dlat_feedback
set analyze option -auto
set system mode lec
read mapped points some_map_file.map
analyze dc -remove_range_constraint
analyze datapath -module -verbose
usage
analyze datapath -verbose
report unmapped points -summary
report unmapped points -extra -unreachable -notmapped
add compared points -all
compare
checkpoint c.ckpt -replace
usage
report compare data -class nonequivalent -class abort -class notcompared
report verification -verbose
report statistics
vpxmode
[/source]
here is the mapping file
add mapped points some_hierachy/some_module1 some_hierachy/some_module2 -type BBOX BBOX
add mapped points some_hierachy/some_module1 some_hierachy/some_module2 -input_pin module1_pin_name module2_pin_name -replace_pin_mapping -type BBOX BBOX
