This project was aspired by an answer posted on zhihu.com:Why is the rich richer and the poor poorer? – Answer of 崔绍瑄 +20
KWSequence – Javascript Project
本工具的用意是方便数字IC设计工程师绘制自己的电路时序图。 I. 项目目标 提供一个在线生成数字电路仿真波形图的工具，通过输入ASCII字符即可得到对应的波形图，方便大家进行在线交流。本项目一共分为3个阶段。第一阶段的目标是实现一个完全兼容AndyTiming工具ASCII字符命令的在线工具，说白了就是把AndyTiming移植到网页上。第二阶段是扩展阶段，主要是增加部分AndyTiming缺乏支持的功能，例如增强版的Mark标签，不定态的表示，状态转移符号的绘制等等。第三阶段是服务扩展阶段，主要是增加网页的服务功能，例如生成网页嵌入图片的脚本，一键提交图片到公共图库并复制链接等功能。希望大家对本项目的发展多多提出宝贵意见。 II. 项目日志 Day 28.Aug.2016 挖了一个大坑，看什么时候有空填上吧。 Day 11.Nov.2017 哇塞，时隔1年多我终于昨天花了一整天把这个代码完成了，撒花。目前已经完成的是第一阶段，实现了完全兼容AndyTiming的ASCII命令，额外优化增加了Mark标签的功能。 Day 12.Nov.2017 昨天发现在手机上用Safari打开Canvas时是无法长按保存图片的，因此增加了保存图片按钮，同时生成图片的HTML代码，这样大家只需要把这个代码复制到自己的文章里就可以引用图片了。 目前已经支持的符号包括： – 高阻态 ~ 高电平 _ 低电平 / 上升沿 \ 下降沿 [ 数据起始 ] 数据结束 \< 数据起始沿 > 数据结束沿 * 数据变化 : 不定态 | 时间轴标签： 格式为 标签名称@标签所在信号行编号 在正确的位置标注’|’号。 + 时间轴： 格式为 时间单位#时间轴精度 在正确的位置标注‘+’号。 III. 离线使用KWSequence 本工具将在此页面长期不间断更新，但是如果你需要离线使用本工具，可以点击下载KWSequence.html和KWSequence.js到同一个目录下用浏览器打开KWSequence.html即可。 +15-1
Useful Skills of Vim While Coding Verilog
1. 前言 其实很早之前就应该写这篇文章了，只是最近太忙了。这几天看到我只列了一个空标题在这里都有好几个人点进来看过了，感觉做得挺不厚道，想想还是先写一点吧，一方面也是为了表明本文绝对是干货满满，值得期待的，废话不多说了，进入正文。 +140
Syntax Comparison Between SystemC and Verilog
To help those who are very familiar with Verilog to get into SystemC easier, I took some time and made this list. More content is to be added later on. 0-1
KWRisc – SystemC and Verilog Project
In this open source project, I am gonna try to design a RISC cpu core based on an open source ISA named RISC-V. +20
StrictVerilog – JavaScript Project
Couples of days ago, when I was reading a tutorial from EECS, University of California, Berkley, I found some words that I have known for long. It is relatively easy to write legal Verilog code which is probably functionally incorrect. +10
Why All Outputs Turns Red Lines In Simulation
There are always guys who are new to Verilog keep asking me this question: Why are all outputs of my module red lines? At first, I was still very patient and keen on helping them find out the bugs. For red lines stand for unsure state of the signals, and which could result from many […]
Study Note About CDC Issue
Before we start it, I must declare that most contents that I summarized in this article can be derived from this online paper: Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog. If you want to dig into some details that I mentioned in this article, you can read that paper as reference. CDC is […]
How To Use Cadence LEC For Logic Equivalence Check
Conformal ® LEC Logic Equivalence Checker is a trade mark registered by Cadence. I use this tool very often lately to make sure the logic equivalence between RTL code written in both VHDL and Verilog languages. As there are not many tutorials online that talk about this tool, I have to had spent quit a […]
How To Mix VHDL And Verilog In Simulation
I will talk about this topic later. Basically, If you are using VCS, you will need to map the codes that was written in different languages into different libraries by using engines dedicated for different languages before you run any simulation. 00