I know that there are so many available methodologies for IC verification out there, such as UVM, VMM, etc. I also know that many EDA gaints in semiconductor industry like Synopsys and Candence are still trying their best to provide better, faster, more transparent methods (namely some emulators) to make it possible to verify a […]
How To Convert VHDL To Verilog
It is said that, when it comes to the favourite digital RTL design language, most companies in the North America prefer Verilog, whereas many of their European counterparts will choose VHDL. Personally, I know Verilog better than VHDL. More specifically, I could only read VHDL code but not write it. So if I need to […]
Why Do Setup Time And Hold Time Matter
In this article, I am going to talk about the definitions of setup time and hold time, as well as the calculation of circuit’s performance limits where setup time and hold time should be considered.For digital sequential logic design, clock timing is the most critical problem to ensure functional corectness. Basically, the delay path between […]
How To Fast Build Testbench For Module Test
Does an IC designer need to know about verification skills? Personally, I suggest that it is necessary to understand the basic methodologies. To have an in-depth understanding of either VMM/UVM methodology may take three or five months, but to just learn the core idea of how and why to build it can cost you maybe […]
Stop Creating Clocks & Resets Locally
When this topic first came to my mind, I was hanging out on a beach in Tsingtao. It has been so long since the last time when I went to a beach. The warm and overwhelming salty smell of Tsingtao beach reminded me of the old time when I was cycling along the Southampton Water […]
Plane War Game – JavaScript Project
The birth of this project is due to a post on the internet. It was three days back when I was on the commuting tube train, I found someone asked this question — Is This Game Enough As Reference For A Front-end Web Developer Internship? Obviously many people like me were lured to click the post since they […]
One-hot State Machine
When I was checking the source code of ARM7-TDMI, a very unusual state machine caught my attention. It was used in the codes of the ALU’s multipliers. After doing some researches, I finally figured out that it was the so-called ‘One-hot State Machine’. I have heard about this kind of state machine when I was […]
How To Build SystemC Compile Environment
I started learning SystemC yesterday, for I found that it is too difficult to understand ArchC if I don’t study SystemC first. Thankfully I still remember all fundamental grammars of C++, so I could just focus on the different ways of hardware description between SystemC and Verilog. The book I am reading is SystemC片上系统设计-陈曦,徐宁仪. If […]
Open Source ESL Design
作者：Kellen Wang 从今天开始我的职能正式改变了，以前一直专注于RTL实现，现在要转变为更高层次的设计级别——ESL，Electronic System Level。所以只会用verilog恐怕是不行了。在网上搜索了一圈，发现目前中文技术世界里还很少有涉及ESL方面的书，虽然这玩意也出来十几年了，唯一的一本书涉及得也不深。据说ESL从出来的那一天起就一直是雷声大雨点小，各种巨头都纷纷认为它是未来的技术方向，同时都暂时不考虑对它的应用进行深入探索。虽然某些公司已经声称发布了基于ESL方法设计的芯片，但目前还只能说停留在实验室阶段。但是没办法，我是一个不能接受“经验”的人，凡事都应当讲究“方法学”，中文搜索怕是不灵了，只能向外国和尚求经。今天在bing.com搜到了一本好书，比较适合用来研究ESL，发现目前还没有中文译本，决定从今天开始看，在这里对重要内容做一些笔记。好了废话不多说，开始吧。 +20
Computer System Architecture Study Note
作者：Kellen Wang 1. 架构与功耗 在电压给定、工作量给定的情况下，降低计算机频率或许可以降低芯片的表面温度，但完成工作量所花费的实际功耗并不会因此降低。如果真的想降低系统功耗的话，必须在降低工作频率的同时降低系统电压。由于功耗与电压是平方关系，只要电压下降一半，功耗就会下降为之前的四分之一，再乘上频率的同比例降低，整个系统的实际功耗会下降为之前的八分之一。因此20年来系统内核电压一直在不断下降，从5V一直降到现在的1V。 随着制程的不断上升，芯片面积越来越小，散热问题越来越严峻。在解决散热问题之前，时钟频率似乎已经到达了一个瓶颈。因此，从2003年以后系统主频就鲜有上升，一直维持在最高3.3Ghz左右。 +30