To those fellows who are quite familiar with the Linux Shell environment, they must be knowing the ‘open new tab under the same working directory’ function. However, the pre-installed Terminal app on OS X seems like not supporting this function well naturally. Thus for countless times I have to find all the way back to […]
Why All Outputs Turns Red Lines In Simulation
There are always guys who are new to Verilog keep asking me this question: Why are all outputs of my module red lines? At first, I was still very patient and keen on helping them find out the bugs. For red lines stand for unsure state of the signals, and which could result from many […]
How To Use Cadence LEC For Logic Equivalence Check
Conformal ® LEC Logic Equivalence Checker is a trade mark registered by Cadence. I use this tool very often lately to make sure the logic equivalence between RTL code written in both VHDL and Verilog languages. As there are not many tutorials online that talk about this tool, I have to had spent quit a […]
How To Mix VHDL And Verilog In Simulation
I will talk about this topic later. Basically, If you are using VCS, you will need to map the codes that was written in different languages into different libraries by using engines dedicated for different languages before you run any simulation. 00
How To Convert VHDL To Verilog
It is said that, when it comes to the favourite digital RTL design language, most companies in the North America prefer Verilog, whereas many of their European counterparts will choose VHDL. Personally, I know Verilog better than VHDL. More specifically, I could only read VHDL code but not write it. So if I need to […]
Why Do Setup Time And Hold Time Matter
In this article, I am going to talk about the definitions of setup time and hold time, as well as the calculation of circuit’s performance limits where setup time and hold time should be considered.For digital sequential logic design, clock timing is the most critical problem to ensure functional corectness. Basically, the delay path between […]
How To Fast Build Testbench For Module Test
Does an IC designer need to know about verification skills? Personally, I suggest that it is necessary to understand the basic methodologies. To have an in-depth understanding of either VMM/UVM methodology may take three or five months, but to just learn the core idea of how and why to build it can cost you maybe […]
Stop Creating Clocks & Resets Locally
When this topic first came to my mind, I was hanging out on a beach in Tsingtao. It has been so long since the last time when I went to a beach. The warm and overwhelming salty smell of Tsingtao beach reminded me of the old time when I was cycling along the Southampton Water […]
What is Good Verilog Coding Style
Recently, I was asked by my boss to make some rules to regulate the verilog coding style in my team. For confidentiality reasons, I wouldn\’t be able to share the whole pages with you, but still I would like to point out some little tips that I personally strongly recommend you to adopt. I. Example […]