1. 前言 其实很早之前就应该写这篇文章了，只是最近太忙了。这几天看到我只列了一个空标题在这里都有好几个人点进来看过了，感觉做得挺不厚道，想想还是先写一点吧，一方面也是为了表明本文绝对是干货满满，值得期待的，废话不多说了，进入正文。 +140
Syntax Comparison Between SystemC and Verilog
To help those who are very familiar with Verilog to get into SystemC easier, I took some time and made this list. More content is to be added later on. 0-1
KWRisc – SystemC and Verilog Project
In this open source project, I am gonna try to design a RISC cpu core based on an open source ISA named RISC-V. +20
StrictVerilog – JavaScript Project
Couples of days ago, when I was reading a tutorial from EECS, University of California, Berkley, I found some words that I have known for long. It is relatively easy to write legal Verilog code which is probably functionally incorrect. +10
Why All Outputs Turns Red Lines In Simulation
There are always guys who are new to Verilog keep asking me this question: Why are all outputs of my module red lines? At first, I was still very patient and keen on helping them find out the bugs. For red lines stand for unsure state of the signals, and which could result from many […]
Study Note About CDC Issue
Before we start it, I must declare that most contents that I summarized in this article can be derived from this online paper: Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog. If you want to dig into some details that I mentioned in this article, you can read that paper as reference. CDC is […]
How To Use Cadence LEC For Logic Equivalence Check
Conformal ® LEC Logic Equivalence Checker is a trade mark registered by Cadence. I use this tool very often lately to make sure the logic equivalence between RTL code written in both VHDL and Verilog languages. As there are not many tutorials online that talk about this tool, I have to had spent quit a […]
How To Mix VHDL And Verilog In Simulation
I will talk about this topic later. Basically, If you are using VCS, you will need to map the codes that was written in different languages into different libraries by using engines dedicated for different languages before you run any simulation. 00
Real Time Stimulus And Simulation – System Verilog Project
I know that there are so many available methodologies for IC verification out there, such as UVM, VMM, etc. I also know that many EDA gaints in semiconductor industry like Synopsys and Candence are still trying their best to provide better, faster, more transparent methods (namely some emulators) to make it possible to verify a […]
How To Convert VHDL To Verilog
It is said that, when it comes to the favourite digital RTL design language, most companies in the North America prefer Verilog, whereas many of their European counterparts will choose VHDL. Personally, I know Verilog better than VHDL. More specifically, I could only read VHDL code but not write it. So if I need to […]