SystemVerilog – Where Two Linguists Met

Programming Languages, SystemVerilog, Verilog, VHDLSunday August 7th, 2016Wednesday November 29th, 2017

Useful Skills of Vim While Coding Verilog

1. 前言其实很早之前就应该写这篇文章了，只是最近太忙了。这几天看到我只列了一个空标题在这里都有好几个人点进来看过了，感觉做得挺不厚道，想想还是先写一点吧，一方面也是为了表明本文绝对是干货满满，值得期待的，废话不多说了，进入正文。 +140

Project, SystemVerilog, VerilogThursday October 29th, 2015Thursday October 29th, 2015

Real Time Stimulus And Simulation – System Verilog Project

I know that there are so many available methodologies for IC verification out there, such as UVM, VMM, etc. I also know that many EDA gaints in semiconductor industry like Synopsys and Candence are still trying their best to provide better, faster, more transparent methods (namely some emulators) to make it possible to verify a […]

SystemC, SystemVerilog, Verilog, VHDLFriday February 27th, 2015Saturday February 4th, 2017

The Knowledge Base Of A Qualified IC Design Engineer

When I just graduated from school, I deemed myself as an already qualified digital IC design engineer. However, I soon learnt how stupid I was once I started my career as an engineer. I have seen many great engineers in companies, and I have learnt a lot from them. In this article, I would love […]