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I will talk about this topic later. Basically, If you are using VCS, you will need to map the codes that was written in different languages into different libraries by using engines dedicated for different languages before you run any simulation.
I was all tied up for work lately (not able to go back home for 4 weeks by far), so I wouldn't be able to finish this article very soon. But I can tell you the key points that needs for mix-up simulation.
First of all, as VHDL compilation is highly library dependent, we need to compile all verilog code in to specified libraries first. Then we start the simulation based on the libraries instead of source code files or file lists.
