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In this open source project, I am gonna try to design a RISC cpu core based on an open source ISA named RISC-V.
KWRisc – SystemC and Verilog Project
3 thoughts on “KWRisc – SystemC and Verilog Project”
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hey,maybe we can share this project together .with SystemC. I am a master student in XiDian University 。major at the digital IC design. haha, can you tell me more about this project through 429499583@qq.com . thank you ha .谢谢了
this website is an amzaing place !! nice !!
I have ever write a simple MCU project , just 2 pipeline ,about 32 instructions ,correct function with modelsim , haha but , i think this is a very cool job . recently , I read some papers and books about the CPU design .such as 超标量处理器设计 （姚永斌）.Poor English,poor ability, but I believe this is a nice try.