There are always guys who are new to Verilog keep asking me this question: Why are all outputs of my module red lines? At first, I was still very patient and keen on helping them find out the bugs. For red lines stand for unsure state of the signals, and which could result from many […]
Study Note About CDC Issue
Before we start it, I must declare that most contents that I summarized in this article can be derived from this online paper: Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog. If you want to dig into some details that I mentioned in this article, you can read that paper as reference. CDC is […]