Before we start it, I must declare that most contents that I summarized in this article can be derived from this online paper: Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog. If you want to dig into some details that I mentioned in this article, you can read that paper as reference. CDC is […]
Why Do Setup Time And Hold Time Matter
In this article, I am going to talk about the definitions of setup time and hold time, as well as the calculation of circuit’s performance limits where setup time and hold time should be considered.For digital sequential logic design, clock timing is the most critical problem to ensure functional corectness. Basically, the delay path between […]