Mix-up Simulation – Where Two Linguists Met

Idea, Verilog, VHDLMonday November 2nd, 2015Saturday November 14th, 2015

How To Mix VHDL And Verilog In Simulation

I will talk about this topic later. Basically, If you are using VCS, you will need to map the codes that was written in different languages into different libraries by using engines dedicated for different languages before you run any simulation. 00